library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;

entity latch16 is
    port (
        i      : in  std_ulogic_vector(15 downto 0);
        o      : out std_ulogic_vector(15 downto 0);
        clk    : in  std_ulogic;
        rst    : in  std_ulogic;
        enable : in  std_ulogic
        );
end latch16;

architecture Behavioral of latch16 is
    component latch
        port (
            i      : in  std_ulogic;
            o      : out std_ulogic;
            clk    : in  std_ulogic;
				rst	 : in  std_ulogic;
            enable : in  std_ulogic
            );
    end component;
begin
    U0  : latch port map(i(0), o(0), clk, rst, enable);
    U1  : latch port map(i(1), o(1), clk, rst, enable);
    U2  : latch port map(i(2), o(2), clk, rst, enable);
    U3  : latch port map(i(3), o(3), clk, rst, enable);
    U4  : latch port map(i(4), o(4), clk, rst, enable);
    U5  : latch port map(i(5), o(5), clk, rst, enable);
    U6  : latch port map(i(6), o(6), clk, rst, enable);
    U7  : latch port map(i(7), o(7), clk, rst, enable);
    U8  : latch port map(i(8), o(8), clk, rst, enable);
    U9  : latch port map(i(9), o(9), clk, rst, enable);
    U10 : latch port map(i(10), o(10), clk, rst, enable);
    U11 : latch port map(i(11), o(11), clk, rst, enable);
    U12 : latch port map(i(12), o(12), clk, rst, enable);
    U13 : latch port map(i(13), o(13), clk, rst, enable);
    U14 : latch port map(i(14), o(14), clk, rst, enable);
    U15 : latch port map(i(15), o(15), clk, rst, enable);
end Behavioral;

